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Senior Chip Integration Engineer
LOS ANGELES CA 90001
Category: Computing, Publishing
  • Your pay will be discussed at your interview

Job code: lhw-e0-79025328

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  Job posted:   Fri Oct 20, 2017
  Distance to work:   ? miles
       
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Senior Chip Integration Engineer

# Senior Chip Integration Engineer


Job Number: 50160776

Santa Clara Valley, California, United States

Posted: 18-Oct-2017

Weekly Hours: 40.00


**Job Summary**

As a digital IC Design Engineer, the individual's primary responsibility will be RTL design. This will include block/function definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs.


**Key Qualifications**

* Typically requires 8+ years or more experience in digital design including RTL design experience

* Experience in low power design and implementation technique, knowledge of UPF and power intent verification.

* Generation of block and full chip timing constraints

* Flow automation scripts using Perl/Python, Tcl, and shell scripts.

* Power user of industry standard RTL Design & Synthesis tools. Knowledge of Extraction and STA methodology and tools

* Typically requires 8+ years or more experience in digital design including RTL design experience ?Full chip UPF experience desirable

* Experience in hands-on lab evaluation ?Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation ?**Description**

oSupporting all design integration activities like Lint, CDC, Synthesis, UPF and ECO

oWorking with Physical Design Team on STA, physical, power and logical issues



**Education**

MSEE


**Additional Requirements**



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